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SILICON DESIGNS, INC
! SENSOR: Capacitive Micromachined Nitrogen Damped Hermetically Sealed ! Digital Pulse Density Output ! Fully Calibrated ! Responds to DC & AC Acceleration ! -55 to +125 EC Operation ! +5 VDC, 2 mA Power (typical) ! Non-Standard g Ranges Available ! Integrated Sensor & Amplifier ! LCC or J-Lead Surface Mount Package ! Serialized for Traceability ! TTL/CMOS Compatible ! No External Reference Voltage ! Easy Interface to Microprocessors ! Good EMI Resistance ! RoHS Compliant
Model 1010 DIGITAL ACCELEROMETER
ORDERING INFORMATION
Full Scale Acceleration 2 g 5 g 10 g 25 g 50 g 100 g 200 g Hermetic Packages 20 pin LCC 20 pin JLCC 1010L-002 1010J-002 1010L-005 1010J-005 1010L-010 1010J-010 1010L-025 1010J-025 1010L-050 1010J-050 1010L-100 1010J-100 1010L-200 1010J-200
DESCRIPTION
The Model 1010 is a low-cost, integrated accelerometer for use in zero to medium frequency instrumentation applications. Each miniature, hermetically sealed package combines a micro-machined capacitive sense element and a custom integrated circuit that includes a sense amplifier and sigma-delta A/D converter. It is relatively insensitive to temperature changes and gradients. Each device is marked with a serial number on its bottom surface for traceability. An optional calibration test sheet (1010-TST) is also available which lists the measured bias, scale factor, linearity, operating current and frequency response.
OPERATION
The Model 1010 produces a digital pulse train in which the density of pulses (number of pulses per second) is proportional to applied acceleration. It requires a single +5 volt power supply and a TTL/CMOS level clock of 100kHz1MHz. The output is ratiometric to the clock frequency and independent of the power supply voltage. Two forms of digital signals are provided for direct interfacing to a microprocessor or counter. The sensitive axis is perpendicular to the bottom of the package, with positive acceleration defined as a force pushing on the bottom of the package. External digital line drivers can be used to drive long cables or when used in an electrically noisy environment.
APPLICATIONS
COMMERCIAL ! Automotive Air Bags Active Suspension Adaptive Brakes Security Systems ! Shipping Recorders ! Appliances INDUSTRIAL ! Vibration Monitoring ! Vibration Analysis ! Machine Control ! Modal Analysis ! Robotics ! Crash Testing ! Instrumentation
Silicon Designs, Inc. ! 1445 NW Mall Street, Issaquah, WA 98027-5344 ! Phone: 425-391-8329 ! Fax: 425-391-0446 web site: www.silicondesigns.com [page 1] Mar 07
Model 1010 Digital Accelerometer
SIGNAL DESCRIPTIONS
VDD and GND (power): Pin 14 (VDD) & pin 19 (GND). Additionally tie pins 3 & 11 to VDD & pins 2, 5, 6 & 18 to GND. CLK (input): Pin 8. Reference clock input. This hysteresis threshold input must be driven by a 50% duty cycle square wave signal. Factory Calibration is performed at 250 kHz which is the recommended clock frequency for best results. Operation at frequencies as low as 100 kHz or as high as 1 MHz are possible, however a slight bias shift may result. CNT (output): Pin 10. Count output. A return-to-zero type digital pulse stream whose pulse width is equal to the input CLK logic high time. The CNT pulse rate increases with positive acceleration. The device experiences positive (+1g) acceleration with its lid facing up in the earth's gravitational field. ___ signal is meant to drive an up-counter directly. This DIR and DIR (output): Pins 12 & 16 respectively. Direction output. This output is updated at the fall of each clock cycle. It is high during clock cycles when a high going CNT pulse is present and low during cycles when no CNT pulse is present. A non-return-to-zero signal meant to control the count direction (i.e. up or down) of a counter. DIR can be low pass filtered ___ to produce an analog measure of the acceleration. DIR is the complement of DIR and is provided for use in driving differential transmission lines. DV (input): Pin 4. Deflection Voltage. Normally left open. A test input that applies an electrostatic force to the sense element, simulating a positive acceleration. The nominal voltage at this pin is aVDD. DV voltages higher than required to bring the output to positive full scale may cause device damage. VR (input): Pin 3. Voltage Reference. Tie directly to VDD (+5V). A 0.1F bypass capacitor is recommended at this pin. CLK/2 (output): Pin 15. Clock divided by 2. A buffered clock output whose frequency equals CLK divided by 2.
PERFORMANCE - by Model: VDD=VR=5.0 VDC, FCLK=250kHz, TC=25EC.
MODEL NUMBER Input Range Frequency Response (Nominal, 3 dB) Sensitivity (FCLK=250kHz) Max. Mechanical Shock (0.1 ms) 1010x-002 1010x-005 1010x-010 1010x-025 1010x-050 1010x-100 1010x-200 2 5 10 25 50 100 200 0 - 400 0 - 600 0 - 1000 0 - 1400 0 - 1600 0 - 1800 0 - 2000 62.5 25.0 12.5 5.00 2.50 1.25 0.625 2000 5000 UNITS g Hz kHz/g g
PERFORMANCE - all Models: Unless otherwise specified VDD=VR=5.0 VDC, FCLK=250kHz, TC=25EC.
PARAMETER Cross Axis Sensitivity Bias Calibration Error
1
MIN -002 -005 thru -200 -002 -005 thru -200
Bias Temperature Shift (TC= -55 to +125EC) 1 Scale Factor Calibration Error 1, 2 Scale Factor Temperature Shift (TC= -55 to +125EC) 1 Non-Linearity -002 thru -100 (-90 to +90% of Full Scale) 1, 2 -200 Power Supply Rejection Ratio (VDD=VR) Operating Voltage (VDD vs GND) Operating Current (IDD+IVR) 1 Clock Input Voltage Range (with respect to GND) Mass: `L' package (add 0.06 grams for `J' package) Note 1: Tighter tolerances available on special order.
TYP 2 2 1 150 100 1 +300 0.5 0.7
MAX 3 4 2 400 300 2 1.0 1.5 5.5 3
UNITS % % of FCLK (span) (ppm of FCLK)/EC % ppm/EC % of span dB Volts mA
40 4.5 -0.5
5.0 2
VDD+0.5 Volts 0.62 grams Note 2: 100g and greater versions are tested from -65 to +65g.
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
Silicon Designs, Inc. ! 1445 NW Mall Street, Issaquah, WA 98027-5344 ! Phone: 425-391-8329 ! Fax: 425-391-0446 web site: www.silicondesigns.com [page 2] Mar 07
Model 1010 Digital Accelerometer
ABSOLUTE MAXIMUM RATINGS *
Case Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125EC Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125EC Acceleration Over-range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000g for 0.1 ms Voltage on VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V Voltage on Any Pin (except DV) to GND 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Voltage on DV to GND 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mW Note 4: Voltages on pins other than DV, GND or VDD may exceed 0.5 volt above or below the supply voltages provided the current is limited to 1 mA. Note 5: The application of DV voltages higher than required to bring the output to positive full scale may cause device damage. * NOTICE: Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at or above these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. CHARACTERISTICS: VDD=VR=5.0 VDC, TC= -55 to +125EC.
SYMBOL VTVT+ VH VOL VOH II CIO IDD+IVR PARAMETER Negative Going Threshold Voltage (CLK) Positive Going Threshold Voltage (CLK) Hysteresis Voltage (CLK) Output Low Voltage (CNT, DIR, CLK/2) Output High Voltage (CNT, DIR, CLK/2) Input Leakage Current (CLK) Pin Capacitance Operating Current MIN 0.9 0.5 VDD - 0.4 10 10 3 TYP 1.7 3.0 1.3 MAX 3.7 0.4 UNITS V V V V V A pF mA TEST CONDITIONS
2
IOL = 2.0 mA IOH = 2.0 mA VI = 0 to VDD 1 MHz, TA = 25EC FCLK = 250kHz
A.C. CHARACTERISTICS: VDD=VR=5.0 VDC, TC= -55 to +125EC, Load Capacitance=50pF.
PARAMETER CLK input frequency CLK input rise/fall time CLK duty cycle CLK fall to DIR fall CLK fall to DIR rise CLK rise to valid CNT out CLK fall to CNT fall CLK fall to CLK/2 rise/fall MIN 100 45 40 40 40 40 40 TYP 250 50 85 90 90 85 90 MAX 1000 50 55 195 205 230 205 210 UNITS kHz ns % ns ns ns ns ns
+5V 11
8
14 VDD
3 VR
0.1 uF 16 DIR 12 DIR CNT CLK/2 10 15 COMPLEMENT OF DIR TO PULSE COUNTER CLOCK / 2
100 kHz to 1 MHz TEST INPUT
CLK
1010x-xxx
4
DV GND 5 19
2
6
18
RECOMMENDED CONNECTIONS
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
PINOUT (LCC & JLCC)
Silicon Designs, Inc. ! 1445 NW Mall Street, Issaquah, WA 98027-5344 ! Phone: 425-391-8329 ! Fax: 425-391-0446 web site: www.silicondesigns.com [page 3] Mar 07
Model 1010 Digital Accelerometer
USING THE COUNT (CNT) OUTPUT: Pulses from the CNT output are meant to be accumulated in a hardware counter. Each
pulse accumulation or sample, reflects the average acceleration (change in velocity) over that interval. The sample period or "gate time" over which these pulses are accumulated determines both the bandwidth and quantization of the measurement.
Quantization (g' s) =
g SPAN * f SR fCLK
1 g FORCE f CNT = f CLK + 2 g SPAN f 1 g FORCE = g SPAN CNT - f CLK 2
Where: gSPAN = 2 * ( full scale acceleration in g' s) f SR = CNT sample rate in Hertz fCLK = accelerometer clock rate in Hertz fCNT = CNT pulse rate in pulses / sec g FORCE = acceleration in gravity units 1 g = 9.8085 m / s2 or 32.180 ft / s2
The first equation above shows that as the sample rate is reduced (i.e. a longer sample period), the quantization becomes finer but bandwidth is reduced. Conversely, as the sample rate is increased, quantization becomes coarser but the bandwidth of the measurement is increased. The second and third equations show how the CNT pulse frequency equates to the applied g-force. When using a frequency counter to monitor the CNT output pulse rate, a counter with a DC coupled input must be used. The CNT output is a return-to-zero signal whose duty cycle varies from zero to fifty percent, from minus full scale to positive full scale acceleration. A frequency counter with an AC coupled input will provide an erroneous reading as the duty cycle varies appreciably from fifty percent. The figure to the left illustrates how the CNT and DIR outputs vary as the accelerometer is subjected to accelerations from minus full scale (-FS) to plus full scale (+FS).
DEFLECTION VOLTAGE (DV) TEST INPUT: This test input applies an electrostatic
force to the sense element, simulating a positive acceleration. It has a nominal input impedance of 32 k and a nominal open circuit voltage of aVDD. For best accuracy during normal operation, this input should be left unconnected or connected to a voltage source equal to a of the VDD supply. The change in output pulse rate (f) is proportional to the square of the difference between the voltage applied to the DV input (VDV) and aVDD. Only positive shifts in the output pulse rate may be generated by applying voltage to the DV input. When voltage is applied to the DV input, it should be applied gradually. The application of DV voltages greater than required to bring the output to positive full scale may cause device damage. The proportionality constant (k) varies for each device and is not characterized.
1 f k VDV - VDD 3
2
ESD and LATCH-UP CONSIDERATIONS: The model 1010 accelerometer is a CMOS device subject to damage from large electrostatic discharges. Diode protection is provided on the inputs and outputs but care should be exercised during handling to assure that the device is placed only on a grounded conductive surface. Individuals and tools should be grounded before coming in contact with the device. Do not insert the model 1010 into (or remove it from) a powered socket.
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
Silicon Designs, Inc. ! 1445 NW Mall Street, Issaquah, WA 98027-5344 ! Phone: 425-391-8329 ! Fax: 425-391-0446 web site: www.silicondesigns.com [page 4] Mar 07
Model 1010 Digital Accelerometer
BIAS STABILITY CONSIDERATIONS
Bias temperature hysteresis can be minimized by temperature cycling your model 1010 accelerometer after it has been soldered to your circuit board. If possible, the assembled device should be exposed to ten cycles from -40 to +85EC minimum (-55 to +125EC recommended). The orientation to the Earth's gravitational field during temperature cycling should preferably be in the same orientation as it will be in the final application. The accelerometer does not need to have power applied during this temperature cycling.
PACKAGE DIMENSIONS
"L" SUFFIX PACKAGE (20 PIN LEADLESS CERAMIC CHIP CARRIER)
*T *M C F K
DIM A B C D E F G H J K L *M N P R *T *U
A
E
Positive Acceleration
TERMINAL 20 TERMINAL 1
A
D
G
"J" SUFFIX PACKAGE (20 PIN LEADED CHIP CARRIER)
R
N
INCHES MIN MAX 0.342 0.358 0.346 0.378 0.055 TYP 0.095 0.115 0.085 TYP 0.050 BSC 0.025 TYP 0.050 TYP 0.004 x 45 0.010 R TYP 0.016 TYP 0.048 TYP 0.050 0.070 0.017 TYP 0.023 R TYP 0.085 TYP 0.175 TYP
MILLIMETERS MIN MAX 8.69 9.09 8.79 9.60 1.40 TYP 2.41 2.92 2.16 TYP 1.27 BSC 0.64 TYP 1.27 TYP 0.10 x 45 0.25 R TYP 0.41 TYP 1.23 TYP 1.27 1.78 0.43 TYP 0.58 R TYP 2.16 TYP 4.45 TYP
*U
L
J P B H
NOTES: 1. * DIMENSIONS 'M', 'T' & 'U' LOCATE ACCELERATION SENSING ELEMENT'S CENTER OF MASS . 2. LID IS ELECTRICALLY TIED TO TERMINAL 19 (GND). 3. CONTROLLING DIMENSION: INCH. 4. TERMINALS ARE PLATED WITH 60 MICRO-INCHES MIN GOLD OVER 80 MICRO-INCHES MIN NICKEL. (THIS PLATING SPECIFICATION DOES NOT APPLY TO THE METALLIZED PIN-1 IDENTIFIER MARK ON THE BOTTOM OF THE J-LEAD VERSION OF THE PACKAGE). 5. PACKAGE: 90% MINIMUM ALUMINA (BLACK), LID: SOLDER SEALED KOVAR.
SOLDERING RECOMMENDATIONS:
RoHS Compliance: The model 1010 does not contain elemental lead and is RoHS compliant. WARNING: If no-lead solder is to be used to attach the device, we do not recommend the use of reflow soldering methods such as vapor phase, solder wave or hot plate. These methods impart too much heat for too long of a period of time and may cause excessive bias shifts. For no-lead soldering, we only recommend the manual "Solder Iron Attach" method (listed on the next page of this data sheet). We also do not recommend the use of ultrasonic bath cleaners because these models contain internal gold wires that are thermo sonically bonded.
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
Silicon Designs, Inc. ! 1445 NW Mall Street, Issaquah, WA 98027-5344 ! Phone: 425-391-8329 ! Fax: 425-391-0446 web site: www.silicondesigns.com [page 5] Mar 07
Model 1010 Digital Accelerometer
SOLDERING RECOMMENDATIONS (continued):
Reflow of Sn62 or Sn63 type solder using a hotplate is the preferred method for assembling the model 1010 surface mount accelerometer to your Printed circuit board. Hand soldering using a fine tipped soldering iron is possible but difficult without a steady hand and some form of visual magnification due to the small size of the connections. When using the hand solder iron method, it's best to purchase the J-Leaded version (1010J) for easier visual inspection of the finished solder joints. Pre-Tinning of Accelerometer Leads is Recommended: To prevent gold migration embrittlement of the solder joints, it is best to pre-tin the accelerometer leads. We recommend tinning one lead at a time, to prevent excessive heating of the accelerometer, using a fine-tipped solder iron and solder wire. The solder bath method of pre-tinning is not recommended due to the high degree of heat the interior of the device gets subjected to which may cause permanent shifts in the bias and/or scale factor. Hotplate Attach Method using Solder Paste or Solder Wire: Apply solder to the circuit board's pads using Sn62 or Sn63 solder paste or pre-tin the pads using solder and a fine tipped soldering iron. If pre-tinning with an iron, apply flux to the tinned pads prior to placing the components. Place the accelerometer in its proper position onto the pasted or tinned pads then place the entire assembly onto a hotplate that has been pre-heated to 250EC. Leave on hotplate only long enough for the solder to flow on all pads (DO NOT OVERHEAT!) Solder Iron Attach Method using Solder Paste: Apply solder paste to the circuit board's pads where the accelerometer will be attached. Place the accelerometer in its proper position onto the pasted pads. Press gently on the top of the accelerometer with an appropriate tool to keep it from moving and heat one of the corner pads, then an opposite corner pad with the soldering iron. Make sure the accelerometer is positioned so all 20 of its connections are centered on the board's pads. Once the two opposite corner pads are soldered, the part is secure to the board and you can work your way around soldering the remaining 18 connections. Allow the accelerometer to cool in between soldering each pin to prevent overheating. Solder Iron Attach Method using Solder Wire: Solder pre-tin two opposite corner pads on the circuit board where the accelerometer will be attached. Place the accelerometer in its proper position onto the board. Press gently on the top of the accelerometer and heat one of the corner pads that was tinned and the part will drop down through the solder and seat on the board. Do the same at the opposite corner pad that was tinned. Make sure the accelerometer is positioned so all 20 of its connections are centered on the board's pads. Once the two opposite corner pads are soldered, the part is secure to the board and you can work your way around soldering the remaining 18 connections. Allow the accelerometer to cool in between soldering each pin to prevent overheating. LCC & JLCC Solder Contact Plating Information: The plating composition and thickness for the solder pads and castellations on the "L" suffix (LCC) package are 60 to 225 micro-inches thick of gold (Au) over 80 to 350 micro-inches thick of nickel (Ni) over a minimum of 5 micro-inches thick of moly-manganese or tungsten refractory material. The leads for the "J" suffix (JLCC) package are made of an Iron-Nickel sealing alloy and have the same gold over nickel plating thicknesses as for the LCC pads. Recommended Solder Pad Pattern: The recommended solder pad size and shape for both the LCC and J-LCC packages is shown in the diagram and table below. These dimensions are recommendations only and may or may not be optimum for your particular soldering process.
DIM A B C D E F G
inch .230 .430 .100 .033 .050 .013 .120
mm 5.84 10.92 2.54 0.84 1.27 0.33 3.05
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
Silicon Designs, Inc. ! 1445 NW Mall Street, Issaquah, WA 98027-5344 ! Phone: 425-391-8329 ! Fax: 425-391-0446 web site: www.silicondesigns.com [page 6] Mar 07
APPLICATION NOTE
Model 1010 Digital Accelerometer
ACCELERATION MEASUREMENT WITH A MICROCONTROLLER:
The CNT (count) pulse density modulation output of the model 1010 accelerometer was designed to drive the type of hardware pulse counter that is sometimes present in microcontrollers. The schematic (below) shows a model 1010 accelerometer driving the T0 counter of an Intel 80C51 microcontroller. The accelerometer's clock is provided by the Address Latch Enable (ALE) output of the 80C51 after being divided by a factor of four by the two 74HC74 "D-Type" flip/flops. The divide by 4 is needed because the maximum count rate of the 80C51's T0 counter is 1/24th of the 8051's clock oscillator frequency (FOSC) and the frequency of ALE is 1/6th of FOSC. Divisors of greater than four should be used if FOSC is greater than 12 MHz to keep the accelerometer's clock frequency at or below the recommended 1 MHz maximum. Use of ALE for the accelerometer clock is only recommended for applications where no external memory is connected to the 80C51. ALE is missing an output pulse for each MOVX instruction which is used to access external memory. Alternatively, any available clock source asynchronous with the 8051's clock may be used to drive the accelerometer so long as its frequency is between 100 kHz and 1 MHz and is no greater than 1/48th of FOSC.
MODEL 1010 CONNECTION TO A MICROCONTROLLER
To obtain each interval's average acceleration, the software needs to poll counter T0's value at fixed intervals then subtract each new counter value from its previous value to obtain a delta (difference) count for each interval. Of course the software must also account for wraparound of the counter which requires that the counter contain enough bits to prevent more than one counter overflow during each sample period. The delta count relates to the average applied acceleration according to the following equation.
C =
Ag 1 f CLK + 2 g SPAN f SR
Where: C fCLK Ag gSPAN fSR
= the change in the counter's value over each sample interval = the accelerometer's input clock frequency = the average acceleration force in g's during the sample interval = 2 * (full scale acceleration rating of accelerometer) = the software sample rate of the counter in samples/sec
At minus full-scale acceleration, the difference count (C) is zero. Zero acceleration results in a difference count of onehalf of the maximum difference count value; plus full scale acceleration results in the maximum value (fCLK / fSR). The actual difference value achieved at zero acceleration [which will be near 1/2(fCLK / fSR)], may be subtracted from each interval's difference count to obtain the acceleration count in sign-magnitude format.
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
Silicon Designs, Inc. ! 1445 NW Mall Street, Issaquah, WA 98027-5344 ! Phone: 425-391-8329 ! Fax: 425-391-0446 web site: www.silicondesigns.com [page 7] Mar 07
APPLICATION NOTE
Model 1010 Digital Accelerometer
CONVERTING DIR TO AN ANALOG VOLTAGE
It is best to use a model 1210 or 1221 for analog applications but if a proportional analog voltage is desired from a model 1010, one can be easily generated by the connection of a low-pass filter to the DIR output as shown in the schematic (below). The table (at right) lists values for R1 and C2 for various cutoff frequencies (-3 dB frequency). R1 is chosen to be at least 100 times the maximum output impedance of DIR which is 200 . The circuit or instrument that the 0 to +5V analog output is connected to, must have an input impedance at least 100 times the value of R1. This simple passive RC filter can be used as long as it provides sufficient rejection of the switching noise present on the DIR output for the specific application. CUTOFF FREQUENCY (Hz) 200 800 1000 1600 2000 R1 (k ) 36.0 35.7 34.0 30.1 36.0 C2 (F) .022 .0056 .0047 .0033 .0022
SINGLE POLE RC FILTER If greater rejection of switching noise is needed, a two pole active filter can be used as shown in the schematic (below). This circuit has the added advantage of providing a very low output impedance compared with the single pole circuit. Its disadvantages include greater complexity and the need for 1 or 2 additional supply voltages for the op-amp. For both filter types, tight tolerance, temperature stable resistors and capacitors should be used. To reject common mode noise over long signal transmission line lengths, DIR and its complement can be used to drive a pair of wires with a differential filter placed at the far end of the wires.
TWO POLE ACTIVE FILTER
Cutoff Frequency (Hz) 200 800 1000 1600 2000
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
R1 & R2 (k ) 21.5 19.1 18.2 17.4 21.5
R3 (k ) 36.0 43.0 42.2 38.3 36.0
R4 & R5 (k ) 93.1 105 102 93.1 93.1
C6 (F) .012 .0027 .0022 .0015
C7 (F) .068 .018 .015 .010
.0012 .0068
Silicon Designs, Inc. ! 1445 NW Mall Street, Issaquah, WA 98027-5344 ! Phone: 425-391-8329 ! Fax: 425-391-0446 web site: www.silicondesigns.com [page 8] Mar 07
APPLICATION NOTE
Model 1010 Digital Accelerometer
ACCELERATION THRESHOLD DETECTION:
For applications where it is desired to know when acceleration has exceeded a threshold value, the simple circuit shown in the schematic (below) can be used. This circuit uses a 74HC161 synchronous binary counter to detect when the DIR logic output goes high for a minimum of 16 clock cycles in a row. The 74HC74 D-type flip/flop is connected in a "onescatch" configuration so that once the threshold is exceeded, the flip/flop stores the event. The clear input sets the counter value to zero and clears the flip/flop, making the circuit ready to detect the next 16 ones in a row sequence. When driven by the DIR (true) output, this circuit provides a threshold of approximately 7/8ths of full scale (+43.75g for a 50g device). ___ Negative acceleration pulses can be detected by connecting the counter to DIR instead of DIR.
THRESHOLD DETECTION CIRCUIT
SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
Silicon Designs, Inc. ! 1445 NW Mall Street, Issaquah, WA 98027-5344 ! Phone: 425-391-8329 ! Fax: 425-391-0446 web site: www.silicondesigns.com [page 9] Mar 07

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